My study


Graduation thesis: High Speed and High Accuracy Analog Memory System
(Apr., 1999 - May, 2000)

Master course study: Low-Power High-Speed SRAM Circuits


Background:

  Nowadays the performance of LSI (Large-Scale Integration) has been increasing rapidly due to high density and high frequency. On the other hand, power dissipation has also been increasing, which leads to power crisis. Especially for mobile equipments power increasing is urgent problem because much power reduces the life of batteries. The technique of performance improvement with no increasing power is required urgently and we are studying on methods about power reduction on transistor level.

Abstract:

  A novel SRAM cell architecture for low-power high-speed operation is proposed that uses no low-VTH MOSFETfs. A additional n-type MOSFET is connected to the source terminals of the driver MOSFETfs which enables write operation with a little voltage difference between opposite bit lines. Low bit-line swing in write and read cycles reduces the power dissipation drastically. This technique is demonstrated in a 64-K SRAM fabricated in a 0.35-ƒÊm CMOS technology. Power dissipation is reduced by 1/5 in write and read cycles at 1.5V in a HSPICE simulation.

Now under constructing!


Below are papers and slides of my presentations.
Sorry, some of papers are written in Japanese.
Presentation in the Univ. (Dec. 15, 2000) paper 535K Japanese
slide 1,914K
Presentation in the Univ. (Apr. 20, 2001) paper 369K Japanese
slide 2,026K
The 62nd applied physics conference (Sep. 14, 2001) paper 12K Japanese
slide 29K
2001 electronics society of IEICE (Sep. 21, 2001) paper 56K Japanese
slide 408K
2002 Symposium on VLSI Circuits (June 13, 2002) paper 104K
Master Thesis (Feb. 13, 2002) paper 1,696K
slide 2,957K
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